As the integrated circuit industry continues to explore techniques to pack more circuits onto a given semiconductor substrate, more and more thought is devoted to not only orienting the various devices in planar fashion along the surface of the substrate, but also to orienting the devices vertically either by building devices up from the substrate surface or by burying devices in trenches formed within the face of the semiconductor body. The open literature is replete with patents and articles which attest to this trend.
Parallel with an exponential growth in the use of integrated circuits has been the development of numerous types of semiconductor memory devices. Advancements in semiconductor technology have made possible memory chips with over a million locations for storing bits of data information. While each generation of memory chips continues to quadruple the number of available storage locations, the size of the integrated circuit chip must yet be maintained within certain limits to enhance production yield and accommodate conventional packaging schemes.
One common memory cell employed in large monolithic integrated memory chips comprises a dynamic random access memory (DRAM) wherein a bit is represented by a charge stored in a capacitor structure. A majority of DRAMs are fabricated using metal-oxide silicon field-effect transistor (MOSFET) technology. With appropriate voltage adjustments, these circuits can be reduced in area simply by scaling to a smaller dimension. Specifically, all dimensions of the various process masks can be uniformally shrunk so that the resulting circuitry is fabricated in a smaller area on the wafer. The scaling of a MOSFET circuit is effective to reduce the wafer area accommodated by the circuit, i.e., within certain limits.
One obvious limitation on scaling of an integrated circuit is the photolithographic technique used to form and maintain registration of the various masks. Another limitation to fabricating denser DRAM cells is that the capacitance of the storage capacitor must be of at least a specified value. With sufficient capacitance, a charge can be stored in the capacitor and later recovered as a signal of sufficient magnitude to be detectable over noise and other electrical interference. Also, the capacitance of the storage capacitor must be of sufficient value so that memory refresh cycle times do not become appreciable in comparison with normal read and write operations of the memory.
Many different types of semiconductor trench and storage capacitor constructions have been proposed in the art, all aimed at reducing cell size of DRAMs and other circuit components without compromising performance of the circuit. One approach taken in the art to conserving semiconductor wafer area is to form the capacitor storage element under a surface fabricated transistor of the cell. This is accomplished by forming a V-groove in the surface of the substrate, forming the cell transistor in the inclined face of the V-groove, and the capacitor thereunder. This type of device is commonly referred to as a V-MOS device. While the V-groove type device is effective in conserving substrate space, difficulties are encountered in masking and fabricating the irregular contour of the V-groove device.
Another memory cell approach taken in the art is partially depicted in FIG. 1. This DRAM memory cell includes a trench in a silicon substrate "Si" within which a capacitor plate "Poly Node" is formed, along with an isolation oxide "SiO.sub.2 ". Selective silicon epitaxy "Epi Si" is then overgrown to bury the DRAM storage trench. A difficulty with the approach, however, is that as cell density increases (e.g., 64 megabit and greater memory arrays), the technique requires an epi thickness which will result in more lateral epi growth than space allows. With sufficient lateral overgrowth the required self-aligned opening to the buried node ("Poly Node") is lost.
Since trench technology is still developing, a need exists for additional trench structures, particularly new multiple device type trench structures which facilitate fabrication of extremely high density integrated circuits.